Huawei Reveals New Chip Architecture, Targets 1.4nm-Equivalent Performance by 2031

Huawei has unveiled a next-generation semiconductor framework that could redefine how chips are designed and scaled. Moving beyond traditional transistor miniaturisation, the company is betting on innovative architectural approaches to achieve performance levels comparable to 1.4nm technology by 2031.

A New Direction Beyond Moore’s Law

Chinese technology giant Huawei Technologies has introduced a groundbreaking semiconductor scaling framework aimed at overcoming the limitations of conventional chip development. The announcement was made during the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) held in Shanghai.

For decades, the semiconductor industry has relied on Moore’s Law, which focuses on shrinking transistor sizes to boost performance and efficiency. However, as physical limits approach, further miniaturisation has become increasingly complex and costly. Huawei’s latest innovation seeks to bypass these constraints by introducing an alternative methodology.

At the core of this strategy is a concept known as the Tau Scaling Law, which shifts the focus from physical scaling to time-based performance optimisation. Rather than simply making transistors smaller, Huawei’s framework enhances how quickly signals propagate and how efficiently systems operate over time.

Tau Scaling Law: Redefining Chip Performance

The Tau Scaling Law represents a significant departure from traditional semiconductor thinking. Instead of measuring progress solely by transistor density, it introduces the idea of “time scaling” as a key metric.

This approach allows improvements in:

• Signal transmission speed
• Operational efficiency
• Overall system performance

Huawei claims that this methodology has already been implemented across 381 chips developed and mass-produced over the past six years. This demonstrates that the framework is not just theoretical but has practical, real-world applications.

By focusing on time efficiency rather than just size reduction, Huawei aims to extend the life of semiconductor innovation even as traditional scaling methods slow down.

Introduction of LogicFolding Architecture

Alongside the Tau Scaling Law, Huawei also unveiled a new chip design methodology called LogicFolding architecture. This architecture is designed to optimise how electronic signals move through circuits.

Key benefits of LogicFolding include:

• Reduced electrical resistance
• Lower capacitance during signal transmission
• Improved energy efficiency
• Enhanced transistor density

By reorganising circuit pathways and “folding” logic structures more efficiently, the architecture minimises delays and energy losses. This results in faster and more efficient chips without requiring extreme transistor miniaturisation.

Huawei has confirmed that its upcoming Kirin processors, expected later this year, will be the first commercial products to integrate the LogicFolding architecture.

Next-Generation Kirin Chips to Lead Adoption

The company’s next-generation Kirin processors will serve as the first real-world demonstration of these innovations. These chips are expected to showcase the advantages of both Tau Scaling Law and LogicFolding architecture.

Huawei executives hinted at a significant leap in performance, suggesting that the upcoming chips could rival or even surpass current industry standards. The integration of these technologies is expected to deliver improvements in:

• Processing speed
• Power efficiency
• AI performance capabilities

The company has positioned these processors as a major milestone in its semiconductor roadmap.

Building a Self-Reliant Semiconductor Ecosystem

Huawei’s advancements come amid ongoing geopolitical challenges and restrictions that have limited its access to foreign semiconductor technologies. In response, the company has spent the past six years building a comprehensive domestic chip ecosystem.

This includes:

• Development of electronic design automation (EDA) tools
• Creation of proprietary chip design methodologies
• Strengthening local manufacturing capabilities

According to company leadership, what was initially expected to take a decade has been achieved in just six years. This accelerated progress highlights Huawei’s determination to reduce dependence on external suppliers and establish technological independence.

Long-Term Vision: 2026 to 2035

Huawei has outlined an ambitious roadmap extending over the next decade. The company plans to evolve its architecture from localized optimisations to full-scale system-wide enhancements.

Future developments will focus on:

• Expanding from critical path folding to full-system folding
• Enhancing integration across hardware and software layers
• Optimising performance from device level to complete systems

By 2031, Huawei aims to achieve performance levels equivalent to 1.4nm semiconductor technology—without relying solely on physical transistor scaling.

Looking further ahead to 2035, the company expects continued growth in:

• Transistor density
• Operating frequencies
• Overall chip performance

This long-term strategy positions Huawei as a strong contender in the global semiconductor race.

Growing Confidence in AI Chip Capabilities

Huawei also emphasised its ambitions in artificial intelligence (AI) computing. The company expressed confidence that its new chips can compete with leading global solutions, particularly in AI workloads.

Key focus areas include:

• Low-latency processing
• High-performance computing
• Scalable AI system deployment

Huawei aims to deliver AI chips capable of supporting large-scale applications while maintaining efficiency and reliability. This is particularly important as demand for AI-driven technologies continues to surge worldwide.

Implications for the Semiconductor Industry

Huawei’s approach signals a broader shift in the semiconductor industry. As traditional scaling methods reach their limits, companies are increasingly exploring alternative paths to sustain innovation.

The introduction of concepts like Tau Scaling Law and LogicFolding architecture could inspire new research directions and redefine how performance improvements are achieved.

If successful, Huawei’s strategy may:

• Extend the relevance of existing fabrication technologies
• Reduce reliance on extreme lithography advancements
• Encourage innovation in chip architecture design

This could reshape the competitive landscape and open new opportunities for technological advancement.

Conclusion

Huawei’s latest announcement represents a bold attempt to redefine the future of semiconductor technology. By moving beyond conventional scaling methods and embracing innovative architectural solutions, the company is positioning itself at the forefront of next-generation chip development.

With its focus on time-based scaling, advanced chip design, and self-reliance, Huawei aims to overcome current industry limitations and deliver cutting-edge performance. The coming years will be crucial in determining whether these ambitious goals can be fully realised.